1. Field
This disclosure relates generally to integrated circuits, and more specifically, to a multi-processor system-on-a-chip (SoC) data processing system having synchronized exit from debug mode and method therefor.
2. Related Art
A system-on-a-chip can include a number of processors and other master and peripheral cores. When debugging the system, individual units, such as the processor cores and peripheral units may enter a debug halted mode due to either a system event, or by command of an external hardware debugging tool. The individual units may enter debug mode at varying times and due to differing events.
Debugging may be performed in accordance with various procedures and interface architectures. One common interface architecture and protocol is defined by IEEE standard 1149.1, also known and JTAG. The JTAG standard is suitable for single core integrated circuits and multiple core integrated circuits. In a multiple core integrated circuit, each core is provided with a TAP (test access port) controller. A test path, or scan chain, is formed through the TAP circuits of each of the cores. The length of the test path is determined by the number of serially-interconnected cores or other units. A top-level TAP controller is used to control the interconnection of cores and other units for debugging operations by interconnecting, or “linking” one or more individual TAP controllers in a serial fashion.
Once an entry into debug mode occurs for one or more units, the external hardware debugging tool may perform serial scan or other operations to query the state of the units, either individually, or in groups. These accesses are performed using a JTAG scan sequence to access the individual JTAG TAP controllers within the individual units. The hardware debugging tool utilizes the top-level TAP controller to select individual unit TAP controllers for access. Accesses to units may be individual accesses, in which only a single unit TAP controller is connected, or may be done with a common group of accesses by concatenating multiple unit TAP controllers to a single long instruction register (IR) and data register (DR).
During the debugging session, individual cores or units that are in debug mode may be queried and controlled by the hardware debugger. When debugging is completed, the hardware debugging tool releases, or reactivates, the units which are currently in debug mode to resume active processing. The external debugging tool may release only one unit, a subset of units, or all of the units. It may be necessary to reactivate the units in a synchronized manner in order to provide a known boundary for re-activation. Reactivation controls can vary, depending on the type of unit. For some units, a JTAG debug “GO” IR command is used, in which the JTAG interface of the unit receives a JTAG IR instruction to cause the unit to exit debug mode. Other units on the SoC may provide a hardware signal that is driven by logic within the SoC to cause exit from debug mode.
For reactivation of the units, the JTAG TAP controllers of the halted units are reconfigured into a single long serial scan chain of TDI and TDO signals via a TAP linking module. The TAP linking module effectively concatenates the selected individual scan chains. Then the hardware debugging tool determines the individual instructions required for each of the various devices and their order in the scan chain. Because each individual unit could have a unique instruction, instruction length, or other sequence for exiting debug mode, the debugging tool has a complex task for forming a single potentially very long pseudo-instruction to control all of the currently halted units. In addition, the linking control information used by the TAP linking logic is also complicated because any possible combination of units must be supported.
Therefore, what is needed is a simpler system and method for synchronously exiting debug mode in a multi-processor SoC.